IBM’s Sub‑1 nm NanoStack Chip Could Cut AI Power Use by Two‑Thirds

IBM unveiled a new chip design that could pack 100 billion transistors onto a wafer the size of a fingernail, a leap that drastically boosts performance while cutting power consumption.

The breakthrough, called NanoStack, replaces the conventional horizontal transistor layout with a vertical “skyscraper” configuration, achieving a theoretical footprint equivalent to 0.7 nm – the world’s first sub‑1 nm technology.

In laboratory tests, the prototype performed 50 % faster than IBM’s own 2 nm chips while using 70 % less energy. For data centres that power generative AI models, this could translate into a two‑thirds reduction in electrical demand, as well as lower cooling requirements, directly shrinking the sector’s carbon footprint.

The 3D stacking approach, however, introduces new challenges. Heat dissipation grows with layer depth, and ultra‑thin separation may cause transistors to fail to switch off. Nonetheless, experts view NanoStack as the most ambitious route toward sustainable silicon.

While the technology is still years away from commercial production, IBM’s announcement signals a crucial shift in the semiconductor industry: prioritising compactness and energy efficiency to support the rapid expansion of AI and the broader digital economy with minimal environmental impact.